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  low - noise, matched dual monolithic transistor MAT02 1.0 scope this specification documents the detail requirements for space qualified product manufactured on analog devices, inc.'s qml certified line per mil - prf - 38535 level v except as modified herein. the manufacturing flow described in the standard spa ce level products program brochure is to be considered a part of this specification http://www.analog.com/aerospace this data sheet specifically details the space grade version of this product. a more de tailed operational description and a complete datasheet for commercial product grades can be found at www.analog.com/MAT02 2.0 part number . the complete part number(s) of this specification follow: part number des cription MAT02 - 903h low - noise, matched dual monolithic transistor 2.1 case outline . letter descriptive designator case outline (lead finish per mil - prf - 38535) h macy1 - x6 6 - lead can package (to) figure 1 - terminal connections . 3.0 absolute maximum ratings . ( t a = 25c, unless otherwise noted) col l ector to base voltage (bv cbo ) ................................ ................................ .................. 40v collector to emitter voltage (bv ceo ) ................................ ................................ .............. 40v collector to collector voltage (bv cc ) ................................ ................................ ............. 40v emitter to emitter voltage (bv ee ) ................................ ................................ ................... 40v collector current (i c ) ................................ ................................ ................................ .... 20ma emitter current (i e ) ................................ ................................ ................................ ....... 20ma t otal power dissipation 1/ ................................ ................................ ........................ 500mw operating ambient temperature range ................................ ............................. - 55 to +125c storage temperature range ................................ ................................ ......... - 65c to +150c lead temperature (soldering, 60 sec) ................................ ................................ ........ +300c dice junc tion temperature ................................ ................................ ......................... +150c 1/ rating applies to applications not using heat sin king, device is free air only.
MAT02s* product page quick links last content update: 11/29/2017 comparable parts view a parametric search of comparable parts. documentation data sheet ? MAT02s: low noise, matched dual monolithic transistor aerospace data sheet design resources ? MAT02s material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all MAT02s engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
MAT02 3.1 thermal characteristics : thermal resistance, to - 78 (h) package junction - to - case ( ? jc ) = 45c/w max junction - to - ambient ( ? ja ) = 150c/w max derate linearly at 6.67 mw/c for ambient temperatures above 70c. terminal connections 1/ terminal 6 lead to 1 c1 2 b1 3 e1 4 e2 5 b2 6 c2 1/ substrate is connected to case on to - 78 package. substrate is normally connected to the most negative circuit potential, but can be floated. table i par ameter see notes at end of table symbol conditions 1/ sub - group limit min limit max units current gain h fe i c = 1ma; v cb = 0v, 40v 1 500 2, 3 275 i c = 100 ? a; v cb = 0v, 40v 1 500 i c = 100 ? a; v cb = 15v 2, 3 225 i c = 10 ? a; v cb = 0v, 40v 1 400 i c = 10 ? a; v cb = 15v 2, 3 175 i c = 1 ? a; v cb = 0v, 40v 1 300 i c = 1 ? a; v cb = 15v 2, 3 150 current gain match 2/ ? h fe i c =10 ? a,100 ? a,1ma; v cb =0v 1 2 % offset voltage v os v cb = 0v 1 50 ? v 2, 3 80 offset voltage vs. temperature 5/ tcv os v cb = 0v 0.3 ? v/c offset voltage vs. v cb 3/ ? v os / ? v cb v cb = 0v, 40v 1 25 ? v offset voltage vs. collector current ? v os / ? i c v cb = 0v; i c = 10 ? a, 1m a 1 25 input offset current i os v cb = 0v, 40v 1 0.6 na 2, 3 9.0 offset current vs. v cb ? i os / ? v cb v cb = 0v, 40v 1 70 pa/v bulk emitter resistance r be 1 0.5 ? ?
MAT02 table i(contd) parameter see notes at end of table symbol conditions 1/ sub - g roup limit min limit max units collector base leakage current i cbo v cb = 40v 1 200 pa collector emitter leakage current 4/ i ces v ce = 40v, v be = 0v 1 200 collector - collector leakage current 4/ i cc v cc = 40v 1 200 bias current i b v cb = 0v, 40 v 1 25 na 2, 3 60 collector saturation voltage v ce sat i c = 1ma, i b = 100 ? a 1 0.1 v breakdown voltage bv ceo i c = 100 ? a 1 40 noise voltage density e n i c =1ma, f o = 10hz 7 2 v cb =0v f o = 100hz 1 f o = 1000hz 1 f o = 10khz 1 table i notes: 1/ v cb = 15v; i c = 10 ? a, unless otherwise spe cified. 2/ current gain match ( ? h fe ) is defined as: 3/ measured at i c = 10 ? a and guaranteed by design over 1 ? a ?? i c ? 1ma. 4/ i cc and i ces are verified by measurement of i cbo . 5/ guaranteed by v os test t = 298k for t a = +25c. hz nv/ c fe b fe h i min ) i ( 100 h ? ? ? ? ? ? ? ? ? ?? ? be os os os v v for t v tcv
MAT02 4.1 electrical test requirements : table ii test requirements subgroups (in accordance with mil - prf - 38535, table iii) interim electrical parameters 1 final electrical parameters 1, 2, 3 1/ 2/ group a test requirements 1, 2, 3 , 7 group c end - point electrical parameters 1 2/ group d end - point electrical parameters 1 group e end - point electrical parameters 1 1/ pda applies to subgroup 1. delta's excluded from pda. 2/ see table iii for delta parameters. see table i for conditions. 4.2 table iii. burn - in test delta limits . table iii test burn - in life test delta title endpoint endpoint limit units h fe @ 1ma 500 420 80 h fe @ 100 ? a 500 410 90 h fe @ 10 ? a 400 300 100 h fe @ 1 ? a 300 180 120 ios 0.6 1.1 0.5 na 5.0 life t est/burn - in circuit: 5.1 htrb is not applicable for this drawing. 5.2 burn - in is per mil - std - 883 method 1015 test condition b. 5.3 steady state life test is per mil - std - 883 method 1005.
MAT02 rev description of change date a initiate aug. 29, 2000 b correc t typo at dice temperature range, change rc package ? jc from 18 to 35c/w, correct typos on table i (subscript), make correction to table i note 3 (change from measured at i c = 10ma and guaranteed by design over 10ma ?? i c ? 1ma to measured at i c = 10 ? a and guaranteed by design over 1 ? a ?? i c ? 1ma), add subgroup 7 for e n , add subgroup 7 to table ii, delete subgroups 4, 5, 6 from table ii. jan. 7, 2002 c update web address. delete burn - in and rad circuits june 20, 2003 d update package offering oct. 10, 2007 e update header/footer & add to 1.0 scope de scription. feb. 25,2008 f r emove operating junction temperature line and change to dice junction temperature (t j ...150c) march 31, 2008 g MAT02 - 913h C removed because its obsolete s ept. 23, 2014


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